The present invention relates generally to input and output protection of integrated circuits, and more specifically to an improved high voltage or electrostatic discharge (ESD) protection network for analog as well as digital integrated circuit devices.
The occurrence of voltage spikes, noise, or other undesirable high voltage signals on the input and outputs of integrated circuits is well known. The prior art has attempted to provide protection for these circuits by using one or more devices to provide current paths between the device pins and one or both voltage supplies to shunt destructive input signals. These destructive input signals are generally caused by electrostatic discharge. The input protection devices are generally used to protect sensitive circuit elements such as the gates of complementary insulated gate field effect transistors. These protection devices have included diodes, zener diodes, lateral bipolar transistors, resistor networks, auxiliary insulative field effect transistors and SCRs.
The use of lateral bipolar transistors for input protection in CMOS ICs is illustrated by U.S. Pat. No. 4,760,433. A resistor-diode input protection circuit which addresses the problem of latch up in CMOS circuits is shown in U.S. Pat. No. 4,143,391. An SCR, Q5 and Q6, is potentially formed at the output side of the input resistor. By designing the circuit without a resistor at the base of Q5, the SCR will not latch up. To prevent the formation of an SCR between the input resistor and the well in which one of the complementary transistors is formed, the base regions of transistors Q7 and Q8 are formed to a large enough length to produce a low current amplification factor or beta. Parasitic SCRs on the output and supply terminal include transistors Q1-Q4. Resistors R5 and R6 are selected to have a very low resistive value to prevent the SCR formed by Q1 and Q2 from latching. These low value resistors also prevent the parasitic SCRs connected to the output pin from latching. As with the parasitic input SCR, the betas are selected to prevent the parasitic transistors from having sufficient gain to latch the output or supply SCRs. U.S. Pat. No. 4,757,363 describes a guard ring used to prevent SCR formation in a CMOS process.
The use of SCRs as input protection devices is shown by a series of patents to Avery and include U.S. Pat. Nos. 4,400,711; 4,484,244; 4,567,500 and 4,595,941. In all of these circuits, the avalanche threshold or breakdown voltage of the SCR has to be high enough not to latch up under normal operating conditions, and the threshold is not altered when power is removed. Thus, these circuits do not provide a low level of threshold protection when the device is not powered up. Also, the leakage currents of the protection structures are not balanced with respect to the input and therefore may not be used with certain kinds of analog circuits. Similarly, the protection provided by these circuits is specifically from an input or output pin to a single supply. None of these circuits will accommodate ESD pulses between all possible pin combinations.
This problem is addressed specifically in U.S. Pat. No. 4,870,530. Between each pin and the substrate pin, an SCR and an anti-parallel diode is provided. This provides current paths in either direction between any pair of input, output, or substrate pins. However, it does not address pin combinations involving the positive supply. As with the Avery patents, the SCR must have a high enough threshold such that it does not latch up during normal operation while still protecting against ESD. Also, the design does not provide for a balance of leakage currents due to the addition of the protective circuitry. This further limits the type of circuits that may incorporate this protective technique.
One group of analog circuits whose performance may be affected by the addition of ESD protection devices are operational amplifiers. For example, Harris Semiconductor operational amplifier HA-5180 has an input bias current specification of one pico-amp or less at room temperature. This type of DC specification places a very stringent requirement on the DC characteristics of the protection circuit, since ideally the addition of a protection circuit should not degrade the original device characteristics. Similarly, added capacitance due to protection circuitry on the input or output terminals would affect an operational amplifier's AC characteristics. For example, Harris Semiconductor operational amplifier HA-2542 has a slew rate in the hundreds of volts per microsecond. This type of AC performance could be drastically degraded if the protection circuit added significant capacitance to certain pins, such as the compensation pin.
Thus it is an object of the present invention to provide an improved ESD protection circuit which will provide low level threshold protection when the circuit is not powered up and high level threshold protection once the circuit is powered up.
Still another object of the present invention is to provide a circuit with such threshold voltage protection features and which is not subject to latch up.
A still further object of the present invention is to provide an ESD protection circuit which can be used on digital as well as analog integrated circuits without effecting the DC or AC operating characteristics of the integrated circuit.
These and other objects are achieved by providing a high voltage protection circuit including a breakdown network connecting a first terminal to be protected and a supply terminal. The breakdown network has a first low threshold value when power is removed from the supply terminal. This allows the formation of a discharge path to occur at a low threshold voltage. In addition, the breakdown network also has a second threshold value higher than the first threshold value when power is applied to the supply terminal. This prevents the formation of a discharge path during normal operation of the circuit to be protected. Thus the network has a lower threshold value when the circuit to be protected is not powered up than it does when the circuit is powered up.
The protection circuit includes anti-latching circuitry connected to the breakdown network for preventing the breakdown network from latching on after or during the time power is applied to the positive and negative terminals. Thus, although the network may come on to provide some ESD protection, it will not latch on when the circuit to be protected is powered.
The breakdown network includes a plurality of diodes and SCRs connecting the first terminal, the positive terminal and the negative terminal. These devices provide protective current paths through forward biased diodes or SCRs for any combination of signals on the first, positive and negative terminals while power is not present on the positive and negative terminals. The leakage current between the first terminal and the positive terminal, and between the first terminal and the negative terminal are of opposite polarity and thus cancel each other while power is applied to the positive and negative terminals. This cancellation effect prevents the ESD protection circuit from altering the normal DC operating characteristics of the first terminal. The breakdown network includes a first SCR having an anode and anode gate connected to the positive terminal, a cathode connected to the terminal to be protected and a cathode gate connected to the negative terminal. The breakdown network also includes a second SCR having a cathode and cathode gate connected to the negative terminal, an anode connected to the terminal to be protected and an anode gate connected to the positive terminal. Thus each SCR is connected in such a manner that it could provide a conduction path for an ESD pulse between two pins. However, this conduction path is prevented from forming by the voltages applied to the gates once the power terminals are activated.
A first resistor connects the anode gate of the first SCR to the positive terminal and a second resistor connects the cathode gate of the second SCR to the negative terminal. The value of the resistors are selected to prevent the respective SCR from turning on when power is applied to the positive and negative terminals while permitting the SCR to turn on when power is removed from the positive and negative terminals. The first and second resistors are either fixed resistors or variable value resistors. A variable value resistor would have a higher resistive value when the power is removed from the positive and negative terminals than the resistive value when power is applied to the positive and negative terminals. The variable resistor could be a field effect transistor having a source drain path connected in series with the gate of the SCR and its gate connected to one of the power terminals.
A first diode can be added having its anode connected to the first SCR's cathode and its cathode connected to the terminal to be protected. Also a second diode can be added having its anode connected to the terminal to be protected and its cathode connected to the second SCR's anode. This increases the breakdown voltages from the positive supply to the first terminal and the first terminal to the negative supply.
A third SCR may be included having a cathode and anode gate connected to the positive terminal, an anode connected to the terminal to be protected and a cathode gate connected to the negative terminal. Also a fourth SCR can be included having a cathode connected to the terminal to be protected, an anode gate connected to the positive terminal and an anode and cathode gate connected to the negative terminal. A common first resistor connects the anode gate of the first and third SCRs to the positive terminal and a second common resistor connects the cathode gate of the second and fourth SCRs to the negative terminal.
To prevent the first SCR from latching on when power is applied to the power terminals, a device is connected between the cathode and cathode gate of the first SCR; and to prevent the second SCR from latching when power is applied to the power terminals, a second device is connected between the anode and anode gate of the second SCR. These devices are respectively a first diode having a cathode connected to the terminal to be protected and an anode connected to the negative terminal and a second diode having a cathode connected to the positive terminal and an anode connected to the terminal to be protected. The diodes may be common P-N diodes, Schottky diodes, or portions of bipolar or MOS transistors.
An ESD protection circuit may be a portion of the integrated circuit of the terminal to be protected or a portion of a second integrated circuit sharing a common housing with the circuit to be protected. A plurality of integrated ESD protection circuits may be provided within the housing for a plurality of leads to be connected. Alternately, the ESD protection circuit may be in its own housing with its external leads connected to the leads of a first housing including the circuit to be protected.